Amd milan, next generation epyc cpus would have 15 dies

It seems that AMD is working on something very interesting. According to sources, they are actively working on a 15-die design for EPYC AMD Milan. Considering that one of these must be an IO die, this implies that there will be at least one Milan variant with 14 dies compared to 8 in Rome.

AMD Milan, Next Generation EPYC CPUs Would Have 15 Dies

According to Wccftech I ask an engineer, some of these 14 dies would be meant to be HBM memory.

8 DDR4 channels only have enough available bandwidth to optimally handle 10 CPU arrays (80 CPU cores) to the maximum. This means that they are looking for an 8 array layout (64 CPU cores) or a 10 array layout when it comes to the CPU side. Leaving the IO array aside, this leaves 6 or 4 dies unaccounted for and will likely end up as HBM memory, according to speculation.

HBM may offer substantial acceleration, but this implies that this particular variant will be using an interposer. In a nutshell, this means that unless AMD decides to delay this variant until DDR5, it is either an 8 + 6 + 1 configuration (CPU + HBM + IO) or a 10 + 4 + 1 configuration (CPU + HBM + IO).

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An interposer-based design with on-board HBM would be able to offer much faster access and transfer times than traditional DDR-based memory, in which the DDR channel can act as a bottleneck. This is going to result in some significant accelerations for applications that rely heavily on memory.

It is worth mentioning that previous leaks have pointed out that AMD Milan has an 8 + 1 design. Depending on how that is interpreted, it could mean that Milan would have two variants. We will keep you informed.

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