Amd could fix epyc rome memory problems with an interposer

AMD returned to competitiveness in the data center market with its EPYC business processors, which are modules of up to four 8-core Zeppelin arrays. Each array has its own built-in north bridge, which controls 2-channel DDR4 memory and a 32-way PCI-Express gen 3.0 root complex. In applications that require heavy use of memory bandwidth, this non-localized memory approach presents design bottlenecks that would be addressed in the new Rome.

AMD EPYC Rome would have a monolithic memory design

The Ryzen Threadripper WX family of processors accentuates many of these bottlenecks, in the case of video encoding applications that require a lot of memory, performance drops are seen as arrays without direct I / O access lack width of memory band. AMD's solution to this problem is to design the CPU dies with a Northbridge disabled. This solution could be implemented in its next second generation EPYC processors, codenamed " Rome ".

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AMD's next-generation MCMs might see a centralized system controller design surrounded by dies, which could all be in a silicon interposer, the same type found in Vega 10 and Fiji GPUs. An interposer is a silicon matrix that facilitates high-density microscopic wiring between the matrices of an MCM. Unlike current generation EPYC processors, this memory interface is truly monolithic, much like the Intel implementation.

The system controller also features a complex PCI-Express gen 4.0 x96 root, which can handle up to six x16 bandwidth graphics cards, or up to twelve on x8. The matrix also integrates the southbridge, known as the Server Controller Hub, which implements common I / O interfaces such as SATA, USB, and other legacy low-bandwidth I / O, in addition to a few other PCIe lines.

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