Amd zen 2 would have double the l3 cache according to sandra

Caching is a very important part of modern processors, and a major change in this part of the chip usually means that big improvements are coming in the overall processor. SANDRA points to strong modifications to the Zen 2 L3 cache.

SANDRA targets 32MB of L3 cache for each 8-core Zen 2 chiplet

An entry in SiSoft's SANDRA database shows data about an AMD EPYC AMD processor and sheds light on the cache hierarchy for this model. Each 64-core EPYC Rome processor is made up of eight Zen 2 eight-core chiplets manufactured at 7nm, which converge into an I / O controller manufactured at 14nm. This controller is responsible for managing the memory and the PCIe connectivity of the processor. The result mentions the cache hierarchy, with 512 KB of dedicated L2 cache per core and "16 x 16 MB of L3 cache. " For the Ryzen 7 2700X, SANDRA reads the L3 cache as "2 x 8MB L3", corresponding to the amount of 8MB L3 per CCX.

We recommend reading our article on AMD EPYC Rome Performance vs. Intel Cascade Lake in 2S

With SANDRA detecting “16 x 16 MB L3” for 64-core Rome, it is highly likely that each of the 8-core chiplets has two 16MB L3 cache parts, and that its 8 cores are split into two four-core CCX cores with 16MB of L3 cache each. This duplication in the L3 cache by CCX could help processors optimize data transfers between the chiplet and I / O to perform better. This is particularly important since the I / O die controls memory with its monolithic 8-channel DDR4 memory controller.

AMD has made profound changes at the architectural level with Zen 2, we will have to wait until they go on sale to see what all these improvements really translate into, but for now it looks quite good.

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