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Epyc milan and genoa, amd gives details on its new server cpus

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AMD revealed some details about the EPYC Milan (Zen 3) architecture and the EPYC Genoa (Zen 4) architecture planned by the company.

EPYC Milan and Genoa, AMD gives details on its new server CPUs

During his presentation, Martin Hilgeman of AMD, Senior Manager of HPC Applications, revealed slides confirming that the next series of EPYC 'Milan' processors will launch on AMD's existing SP3 server socket, support DDR4 memory and offer the same TDP and the same core configurations as the Rome series of processors.

This slide seems to dispel rumors that AMD planned to launch Milan with a 4x SMT implementation, which claimed that Zen 3 would offer users four threads per CPU core. It seems that the main source of Zen 3 performance improvements will come from improvements in IPC and gains in clock speed, rather than increases in core and thread numbers. Hopefully, this means Zen 3 will focus on 'single-core' performance and core architecture improvements.

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Turning to EPYC Genoa (Zen 4), Helgeman claims that Zen 4 is still in the design phase, which means that server manufacturers and other customers have an opportunity to influence Genoa's design. It is also confirmed that this new architecture will be launched with a new SP5 socket, will support a new type of memory (probably DDR5) and will offer users "new capabilities", which have not been revealed.

Internalizing in Zen 3's design, AMD confirmed that Zen 3 would move away from Zen / Zen 2's split cache design, which divided AMD's CPU L3 cache between two quad-core CCXs. This means that AMD could be moving away from its own quad-core CCX design, creating an eight-core CCX design with Zen 3 or a different design.

Rather than offering two 16MB L3 caches (as seen in AMD's current Zen 2 design), AMD's Zen 3 design will offer a combination of "32 + MB" L3 cache across all eight CPU cores. This will reduce potential latencies between the CPU cores in a single die and guarantee better access to the integrated L3 cache for the CPU cores. Also, this cache would be bigger than the view in previous generations.

EPYC Milan would come to us during the second half of 2020.

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