Epyc rome, images and more details about amd's most advanced cpu

AMD's second-generation EPYC Rome processors were released in August, and since then we've been getting more details about the chip itself and its features. The latest I / O array details, including close-ups, have been revealed by Hardwareluxx , giving us a better look at AMD's most innovative server chip to date, comprised of 8.4 billion transistors.

EPYC Rome is made up of 8.34 billion transistors

There have been many details that AMD has recently begun to reveal for its second-generation EPYC Rome processors. AMD EPYC Rome processors are comprised of a 9-matrix design that is also known as MCM (Multi-Chip-Module). The 9 arrays include eight CCDs (Compute Core arrays) and a single IOD (input / output array). Each CCD is made up of two CCX (Compute Core complexes) that include four Zen 2 cores with their own L2 cache and a shared L3 cache. All eight CCDs connect to the I / O array.

Each CCD measures 74mm2 and is made up of 3.9 billion transistors. The IOD featured in Ryzen has a matrix size of 125mm2 and is made up of 2.09 billion transistors. The IOD that appears in the EPYC is made up of 8.34 billion transistors and measures 416 mm2. The IOD combined with the 8 Zen 2 CCD's measure 1008mm2 while it is made up of 39.54 billion transistors.

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Now the IOD that appears on the one is much bigger than the one that appears on Ryzen processors. The chip is PCIe 4.0 compliant, found on the sides of the IOD. The capacity of the second generation EPYC is 162 PCIe tracks. The upper and lower die areas have four channels of 72-bit DDR4 memory.

EPYC Rome is already in use on some of the world's most powerful servers, and AMD hopes to continue to increase its server market share with these chips.

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