Intel shows off its new interconnect architecture for the xeon skylake

Last May the new family of Intel Xeon processors based on the Skylake-SP microarchitecture was announced, these chips will still take time to reach the market but one of their key technologies has already been shown, a new interconnection architecture between its elements that It is designed to offer high bandwidth with low latency and great scalability.

New interconnection bus in Skylake-SP

Akhilesh Kimar, architect of the Skylake-SP design, affirms that the design of multi-chip processors seems a simple task but that it is very complicated due to the need to achieve a very efficient interconnection between all its elements. This interconnection must allow the cores, the memory interface and the I / O subsystem to communicate in a very fast and efficient way so that the data traffic does not diminish the performance.

In previous generations of Xeon, Intel has used a ring interconnect to join all the elements of the processor together, by increasing the number of cores to a great extent, this design has ceased to be efficient due to limitations such as the need to pass the data for "a long way". The new design that debuts in the new generation of Xeon processors provides many more ways that data can travel much more efficiently.

The new Intel interconnect bus makes all the processor elements organized in rows and columns providing direct paths between all the parts of a multi-chip processor and therefore allows a very efficient and fast communication, that is, it achieves a high bandwidth and low latency. This design also has the advantage of being highly modular, making it easy to make very large chips with a large number of elements without compromising communication between them.

Source: hothardware