Pcie 5.0, both cxl 1.1 and ccix already work at 32 gt / s per track

Synopsys demonstrated its CXL solutions as well as CCIX 1.1 over PCIe 5.0 at ArmTechCon 2019. The showcase indicates that the company's IP is up and ready to be licensed by technology manufacturers.

Synopsys demonstrated its CXL solutions as well as CCIX 1.1 over PCIe 5.0

CXL and CCIX are chip-to-chip interconnect protocols for connecting processors to various accelerators that maintain memory and cache consistency at low latencies. Both protocols are designed for heterogeneous systems using traditional CPUs in conjunction with accelerators with scalar, vector, matrix, and spatial architectures.

Both CXL 1.0 / 1.1 and CCIX 1.1 use PCIe 5.0 that runs at 32 GT / s per track and supports different link widths natively. With the same market segment and the same physical interface, the CXL and CCIX protocols present numerous differences in terms of both hardware and firmware / software and therefore will compete with each other. Meanwhile, silicon IP providers are preparing to support both CXL and CCIX as they have a wide range of clients.

Synopsys recently introduced its 16-track DesignWare CXL IP solution for SoCs that will be manufactured using 16nm, 10nm and 7nm FinFET process technologies. Package includes CXL 1.1 compliant driver (supports CXL.io, CXL.cache, CXL.mem protocols), silicon tested PCIe 5.0 driver, silicon tested PCIe 32 GT / s PHY driver, RAS and VC Verification IP.

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The company has yet to formally announce the availability of its IP DesignWare CCIX 1.1 package that will allow the implementation of a CCIX 1.1 over PCIe Gen 5 at a speed of 32 GT / s, but at ArmTechCon the company demonstrated that the solution is already functional, bringing with it many benefits in terms of speed and capacity. We will keep you informed.

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