▷ What are processor lanes and the importance in multi

In this article we will explain what the LANES of the processor are. But before we have to know what are the PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, it is a high-speed computer expansion bus standard, designed to replace older bus standards like PCI, PCI-X and AGP.

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What is the PCI Express interface and how does it work?

PCIe has numerous improvements over older standards, including higher maximum system bus performance, lower I / O pin count, and smaller physical footprint, better performance scaling for bus devices, a More detailed error detection and reporting mechanism (Advanced Error Reporting, AER, and native hot-swap functionality. In addition, the latest revisions to the PCIe standard provide hardware support for I / O virtualization.

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Defined by its number of lanes, the PCI Express electrical interface is also used in a variety of other standards, especially the ExpressCard notebook expansion card interface and the SATA Express and M.2 storage interfaces. The format specifications are maintained and developed by the PCI-SIG (PCI Special Interest Group), a group of more than 900 companies that also maintain the conventional PCI specifications. PCIe 3.0 is the latest standard for expansion cards, which is in production and available on conventional personal PCs.

Point-to-point topology

Conceptually, the PCI Express bus is a high-speed serial replacement of the previous PCI / PCI-X bus. One of the key differences between the PCI Express bus and the older PCI is the bus topology; PCI uses a shared parallel bus architecture, in which the PCI host and all devices share a common set of addresses, data, and control lines. In contrast, PCI Express is based on a point-to-point topology, with separate serial links connecting each device to the root complex. Due to its shared bus topology, access to the oldest PCI bus is arbitrated and limited to one master at a time, in one direction. Also, the older PCI clock scheme limits the bus clock to the slowest peripheral on the bus. In contrast, a PCI Express bus link supports full-duplex communication between two endpoints, with no inherent limitation on simultaneous access through multiple endpoints.

In terms of bus protocol, PCI Express communication is encapsulated in packets. The data packaging and unpacking work and status message traffic is handled by the transaction layer of the PCI Express port. Radical differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors. PCI slots and PCI Express slots are not interchangeable. At the software level, PCI Express maintains backward compatibility with previous PCI versions.

What are Processor PCI Express LANES

The PCI Express link between two devices can consist of one to 32 lanes. On a multi-lane link, the packet data is broken up into lines, and the maximum data throughput is scaled with the overall link width. The lanes count is automatically negotiated during device initialization, and can be restricted by any of the endpoints. For example, a single lane (× 1) PCI Express card can be inserted into a multi-lane slot (× 4, × 8, etc.), and the initialization cycle automatically negotiates the highest count of lanes with mutual support.. The link can be dynamically configured to use fewer lanes, providing fault tolerance in case of faulty or unreliable lanes. The PCI Express standard defines slots and connectors for multiple widths: × 1, × 4, × 8, × 12, × 16, and × 32. This enables the PCI Express bus to serve both cost-sensitive applications where high-end is not required performance as well as critical performance applications such as 3D graphics, networking, and enterprise storage.

A lane consists of two differential signaling pairs, with one pair for receiving data and the other for transmitting. Therefore, each lane is made up of four signal cables or traces. Conceptually, each lane is used as a full-duplex byte stream, transporting data packets in eight-bit “byte” format simultaneously in both directions between the endpoints of a link. PCI Express physical links can contain from one to 32 lanes, more precisely 1, 2, 4, 8, 12, 16 or 32 lanes. Lane counts are written with a prefix “×” (for example, “× 8” represents an eight-lane card or slot), with × 16 being the largest size in common use. The sizes of the lanes are also mentioned through the terms "width" or "through", for example, an eight lane slot could be referred to as "per 8" or as "8 lanes wide".

PCIe lanes are used in some places inside your PC. Your CPU has a certain number of them, at least 16, connected between it and at least one 16x slot on the motherboard. These lanes are typically used for graphics cards, either with a card that uses the entire channel or with multiple cards, each with part of the channel. Some CPUs have more graphics card lanes, some of Intel X series CPUs have up to 40 or more.

Some lanes connect their CPU to the Platform Controller Hub (PCH). Intel calls these lanes DMI, but they are actually the same as PCIe. From the PCH, the PCIe lanes go to its SATA controller, its NVMe-compatible M.2 slot, USB drivers, and various PCIe slots on the motherboard for things like network adapters, TV tuner cards, and more. The PCH serves as a multiplexer and ultimately all of these devices have to share the available DMI lanes when communicating with the CPU or main memory.

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This ends our article on processor LANES and what they are for. Hopefully it has been useful for you.