Tsmc talks about its manufacturing process at 5nm finfet

TSMC's new 7nm FinFET (CLN7FF) manufacturing process has entered the mass production phase, thus smelting is already planning its 5nm process roadmap, which it hopes to have ready sometime in 2020.

TSMC talks about improvements to its 5nm process, which will be based on EUV technology

5nm will be the second TSMC manufacturing process to use Extreme UltraViolet (EUV) lithography, which enables huge increases in transistor density to be driven, with an area reduction of 70% compared to 16nm. The company's first node to use EUV technology will be the 7nm + (CLN7FF +), although EUV will be used sparingly to reduce complexity on its first deployment.

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This will serve as a learning phase for the use of EUV to a large extent in the future 5nm process, which will offer a 20% reduction in power consumption with the same performance, or a 15% performance gain with the same energy consumption, compared to 7nm. Where there will be great improvements with the 5nm, it is in the reduction of the area of ​​45%, which will allow placing 80% more transistors in the same area unit than with the 7nm, something that will allow creating extremely complex chips with sizes much smaller.

TSMC also wants to help architects achieve higher clock speeds, to this end it has stated that a new "Extremely Low Threshold Voltage" (ELTV) mode will allow chip frequencies to increase by up to 25%, although the manufacturer It has not gone into great detail about this technology or what type of chips it can be applied to.

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