Amd zen, new details of architecture improvements

Last Tuesday AMD made a presentation to give more details of its new x86 AMD Zen core architecture and more specifically talked about how a huge improvement in the IPC of 40% has been achieved compared to the excavator cores.

Technical details of the AMD Zen microarchitecture

AMD Zen marks the break with the modular design released with Bulldozer to return to a more traditional approach with full cores, the main improvements of Zen focus on three fundamental areas:

• Performance of the engine itself with completely new jump prediction, the introduction of a micro-op cache and a much wider instruction window than what was present in its predecessors.

• Improvement in the cache system: prefetch and a new cache hierarchy with 8MB of L3 cache data and instructions with the aim of maintaining high engine performance.

• Efficiency: AMD Zen is developed with advanced 14nm FinFET technology and a host of architecture-saving power design techniques that enable it to deliver much higher performance per watt consumed than previous generations.

The Zen microarchitecture is organized into units called CPU-Complex (CCX) that contain a total of four cores and 8 MB of L3 cache. A new approach very similar to the one adopted by Intel in which its cores share the L3 cache and no other element to be completely independent. Zen receives great improvements in all the elements that are part of the computing nucleus to achieve a great improvement in performance.

The following improvement is found in the cache system with a hierarchy very similar to that which was present in Phenom processors with the L3 cache shared by each set of four cores as we have commented before. On the other hand, each core has its own L1 and L2 caches, these being vastly improved compared to those used in Bulldozer. L1 cache is now write-back again and SRAM makes it faster as well as L2.

Another of the great improvements in Zen is the introduction of SMT technology, very similar to Intel's HyperThreading and that allows each core to handle two threads of data to improve performance in multithreaded applications.

We continue with the improvement in energy efficiency thanks to the great advances implemented in the design of the microarchitecture as well as the manufacturing process at 14 nm FinFET, a great step forward compared to the 32 nm SOI of Bulldozer and Piledriver. The components of Zen have greater capacity to adjust their operating frequencies and the new cache system is much more efficient with the use of energy. Finally we talk about the instructions implemented in AMD Zen, the new microarchitecture supports the entire ISA set that Includes VX, AVX2, BMI1, BMI2, AES, RDRAND, sMEP, SHA1 / SHA256, ADX, CFLUSHopt, XSAVEC / XSAVES / XRSTORS and SMAP. Plus, exclusive AMD instructions like CLzero and Coalescing are added.