Ibm would have the key to manufacture chips beyond 7nm

IBM and its 'area selective deposition' seeks to improve manufacturing efficiency at 7nm and beyond

The Big Blue boffins are working in an area called " area selective deposition" which, in their opinion, could help overcome the limitations of lithographic techniques to create patterns on silicon in 7nm processes.

Techniques such as "multi-patterning" helped ensure that ICs continued to scale, but as the chips have shrunk from 28nm to 7nm, chipmakers have had to process more layers with ever smaller features that require more precise placement in patterns.

One of the problems is the alignment between layers is that, when done wrong, it leads to an “edge placement error” (EPE). In 2015, Intel lithography expert Yan Borodovsky noted in the minutes that this was a problem that lithography could not solve.

He suggested that selective area deposition was a better bet, so IBM researchers began to review it.

IBM's new technique would replace Samsung's EUV technology

This could be a successor to EUV lithography, the technique Samsung is preparing for its next 7nm and even 5nm chips. This should not surprise us, as IBM was the first in the world to manufacture chips at a 7-nanometer node back in 2015.

Rudy Wojtecki, a researcher at IBM's Almaden Research Center, said that with traditional manufacturing methods this would require coating a substrate with resistive, modeling the resistive through an exposure step, developing the image, depositing an inorganic film and then removing the resistive to give it a patterned inorganic material.

The group is using one of the three main methods for area-selective deposition, called “deposition of atomic layers”, focusing on the use of “self-assembled monolayers” (SAM).

It all sounds very technical, we know, but it will most likely be the future of CPU manufacturing in the years to come, after 7nm processors hit our PCs, which is not too far off.

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