Micron and cadence update ddr5 status, 36% more performance than ddr4

At the beginning of the year, Cadence and Micron held the first public demonstration of next-generation DDR5 memory. At a TSMC event earlier this month, the two companies provided some updates on the development of the new memory technology.

Micron and Cadence discuss their advances in DDR5 memory

The main feature of DDR5 SDRAM is the capacity of the chips, not just higher performance and lower power consumption. DDR5 is expected to increase I / O rates from 4266 to 6400 MT / s, with a supply voltage drop of 1.1 V and a permitted jitter range of 3%. It is also expected to use two independent 32/40 bit channels per module (without / or with ECC). Additionally, DDR5 will have improved command bus efficiency, better upgrade schemes, and a larger pool of banks for additional performance. Cadence goes on to say that the enhanced functionality of DDR5 will allow 36% higher real-world bandwidth compared to DDR4 even at 3200 MT / s, and once 4800 MT / s the actual bandwidth will be 87% higher. compared to DDR4-3200. Another of the most important characteristics of DDR5 will be the density of monolithic chips beyond 16 Gb.

We recommend reading our post on Intel Core 9000 series supports up to 128 GB of RAM

Leading DRAM manufacturers already have monolithic DDR4 chips with a 16Gb capacity, but those devices cannot deliver extreme clocks due to the laws of physics. Therefore, companies like Micron have a lot of work to do in an attempt to bring together high DRAM densities and performance in the DDR5 era. In particular, Micron is concerned with variable retention time and other atomic-level occurrences, once the production technologies used for DRAM reach 10-12 nm. Simply put, while the DDR5 standard accommodates densities and wedding performance, there is still a lot of magic to be done by DRAM makers.

Micron expects to start production of 16Gb chips using its 'sub-18nm' manufacturing process by the end of 2019, although this does not necessarily mean that the actual applications that have this memory will be available by the end of next year. Cadence has already implemented DDR5 IP (Controller + PHY) using TSMC's N7 (7nm DUV) and N7 + (7nm DUV + EUV) process technologies.

Given the key benefits of DDR5, it is not surprising that Cadence predicts that servers will be the first applications to use the new type of DRAM. Cadence believes that the SoCs of customers using the N7 + process will support it, which essentially means that the chips should hit the market in 2020.

Techpowerup font