▷ Pci express 4.0: everything we know so far

At the beginning of the year, the PCI-SIG standards consortium ratified and published the PCI Express 4.0 specification in version 1.0. This marks the full version of PCIe 4.0, and follows the release of the revision specification of June 0.9 last year. In this articles we are going to analyze everything that is known so far about PCI Express 4.0.

Index of contents

PCI Express 4.0 doubles the bandwidth of the current 3.0 specification

PCI Express is currently the high-speed bus used by almost all high-performance components in computers. Both graphics cards, NVMe SSDs, network cards and many other devices are connected through this advanced interface, hence its great importance. PCI Express 4.0 doubles the 8 GT / s bandwidth per lane of PCIe 3.0, thus offering a transfer rate of 16 GT / s per lane, providing significant performance I / O benefits useful for the storage and high-speed network, as well as artificial intelligence applications. At the same time, PCI-SIG focused on Q2 2019 to release the finalized PCIe 5.0 specification, so PCIe 4.0 will not be as durable a version as PCIe 3.0 has been.

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PCI-SIG has previously maintained a four-year cadence for PCIe 1.0 (2003), PCIe 2.0 (2006), and PCIe 3.0 (2010). Regarding the seven-year delay, PCI-SIG noted that PCIe 3.0 was providing enough bandwidth for some time, ahead of the developments and increasing demands of AI, PCIe NVMe, and 3D XPoint computing workloads, and network speeds, particularly as 10GbE becomes more and more accessible to consumers.

PCI Express 4.0 maintains backward compatibility, and NVMe SSDs will greatly benefit from its benefits

For computing GPUs, PCIe 3.0 bandwidth limitations had already prompted Nvidia to develop its proprietary NVLink interconnect. Consequently, with PCI Express 4.0 and beyond, the PCI-SIG seeks to return to a more normal cadence, especially since they have now solved some of the major technical hurdles, to allow for faster transfer rates through the PCIe 4.0 standard. The other aspect is the nature of the organization. PCI-SIG has almost 800 member companies, of which annually elect a board of directors; For 2017-2018, the Board includes members from AMD, Intel, and Nvidia. By developing and maintaining open PCI specifications, members collaborate on technical committees and working groups, submitting and reviewing changes to specifications. Some of the recent PCI-GIS work is being streamlined in this process.

Once specifications are finalized, members must have products pass interoperability and compliance tests at one of the many PCI-GIS Compliance Workshops throughout the year, so that the product is added to the List of Integrators, which OEMs and system integrators use to choose hardware. For PCIe 4.0, PCI-SIG offered pre-release compliance workshops for the first time, using previous version 0.9, but only at a preliminary level of “FYI Test”. For the rest of the year, PCI-SIG will offer FYI PCIe 4.0 Testing in compliance workshops; PCIe 4.0 is not currently listed in the Official Compliance Program or on the Integrator List.

As in previous PCIe iterations, PCIe 4.0 features backward compatibility, and PCIe 1.x, 2.x, and 3.x cards conform to PCIe 4.0 slots and function normally. PCIe 4.0 also maintains the 128b / 130b encoding of PCIe 3.0, which will continue to be used in PCIe 5.0. Among the other enhancements, various features are more relevant to designers and developers than to end users. As data rates increase, performance variation increases and signal integrity degrades.

Higher performance

With this in mind, PCIe 4.0 offers a lane margin on the PHY receiver, where the PCIe controller obtains the electrical margin information from each PCIe lane to measure the tolerance of variation. PCIe 4.0 also has extended labels and credits, features that work together to mask latency and promote full bandwidth saturation. Other enhancements include reduced overall system latency, I / O virtualization and platform integration, and added bandwidth / bandwidth scalability, as well as improved reliability, availability, and capacity capabilities. service (RAS).

While gaming graphics cards are the most visible PCIe device to consumers, the additional overhead of PCIe bandwidth is unlikely to affect gaming performance, at least right away. However, given the limited amount of available PCIe bandwidth with most consumer CPUs, this will also go a long way towards easing the pressure that the combination of GPUs, an NVMe SSD, and 10GigE networks can be located on the system I / O bandwidth. What may also be relevant is a higher power capacity of the secondary connectors.

As for PCIe 4.0 vendor solutions, Synopsys and Cadence, among others, are developing or offering PHY and 16 GT / s drivers, validation tools and many other applications. The IBM POWER9 has PCIe 4.0 connections and the Intel Falcon Mesa FPGA 10nm supports PCIe 4.0 as a built-in IP block via EMIB. Meanwhile, AMD offers PCIe 4.0 support with its new Radeon Instinct MI50 and MI60. Navi and Zen 2 are also expected to support PCI Express 4.0.

The following table summarizes the most important features of the different versions of PCI Express to date:

Version	Introduction	Transfer by lane	Bandwidth
× 1	× 2	× 4	× 8	× 16
1.0	2003	2.5 GT / s	250 MB / s	0.50 GB / s	1.0 GB / s	2.0 GB / s	4.0 GB / s
2.0	2007	5.0 GT / s	500 MB / s	1.0 GB / s	2.0 GB / s	4.0 GB / s	8.0 GB / s
3.0	2010	8.0 GT / s	984.6 MB / s	1.97 GB / s	3.94 GB / s	7.88 GB / s	15.8 GB / s
4.0	2017	16.0 GT / s	1969 MB / s	3.94 GB / s	7.88 GB / s	15.75 GB / s	31.5 GB / s
5.0	Expected in Q2 2019	32.0 GT / s	3938 MB / s	7.88 GB / s	15.75 GB / s	31.51 GB / s	63.0 GB / s

This concludes our article on the PCI Express 4.0 protocol, we hope it has helped you better understand the importance of this new version of today's most widely used high-speed interface.

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