All the features and news of amd raven ridge

AMD Raven Ridge Features and News

AMD Ryzen 5 2400G and Ryzen 3 2200G are coming to replace Ryzen 5 1400 and Ryzen 3 1200 within the mid-range segment. These two processors are targeted at the price segment below 100 euros and 200 euros, so they are in a very sensitive position regarding the relationship between price and performance. Below we will see some of the decisions that AMD has made with these processors to make them the best offer on the market in their price ranges.

Higher frequencies and a single CCX complex design

AMD Raven Ridge offers a significantly higher base and increases clock speeds at the same recommended price or even lower for 2200G. This decision was made by the observation that PC games are predominantly clock-sensitive, the new manufacturing process at 14nm + has allowed to increase the operating frequencies of the Zen core.

Another important innovation is that Raven Ridge uses a 4 + 0 configuration, so all the cores are in a single CCX. Despite widespread community speculation, AMD's analysis concluded that 2 + 2 vs. 4 + 0 is roughly equivalent on average in over 50 games. The tests concluded that some games benefited from the additional cache of a two CCX configuration, while other games benefited from the lower latency of one CCX regardless of the amount of cache. AMD has decided to take a single CCX approach, which allows for a more compact array size, which is also helped by reducing the L3 cache from 8MB to 4MB.

Improved cache and DDR4 controller to reduce latencies

To compensate for cache reductions, Raven Ridge processors significantly reduce cache and RAM latencies. This change will offer a net positive improvement for highly latency sensitive workloads, especially video games. Related to RAM we also have to mention the inclusion of a new DDR4 controller that allows to reach JEDEC DDR4-2933 frequencies natively, this will allow the Infinity Fabric bus of these processors to operate with a higher bandwidth and lower latency.

I nfinity Fabric is a flexible and consistent interface / bus that enables AMD to quickly and efficiently integrate data between CCX, system memory, and other controllers, such as memory, and the complex I / O and PCIe complexes present in the design of all AMD Ryzen processors. Infinity Fabric also gives Zen architecture powerful command and control capabilities for the smooth operation of AMD SenseMI technology.

The Ryzen processors showed that one of their biggest weaknesses is video games, this is because they are very sensitive to the high latencies of access to the cache and RAM of the first generation of Ryzen. Therefore, Raven Ridge should significantly improve its performance in video games.

Fewer PCI Express lanes to make the product cheaper

PCIe lanes go from x16 to x8 in Raven Ridge, this change makes the processors easier to manufacture, allowing to reduce the cost of sale to the consumer and offer the Ryzen 3 2200G for a price 10 euros lower than the Ryzen 3 1200. This is a change that shouldn't make any difference for mid-range GPUs, which are the ones that will be used alongside these processors. This change also contributes to a smaller and more efficient chip.

We continue to see news of the Raven Ridge processors with a transition to a non-metallic TIM for the 2400G and 2200G, this means that the solder that joins the IHS to the die in the first generation Ryzen has been replaced by a cheaper thermal compound, This further enhances the price competitiveness of Ryzen 2000G series products.

New algorithm for higher turbo frequencies

It is time to talk about Precision Boost 2, one of the most important technologies that are part of SenseMI, and that it is a new algorithm of frequency increase much more linear than the first version of this technology. Precision Boost 2 allows the Raven Ridge to drive more cores, more often, in more workloads. This new algorithm takes into account factors such as the number of cores in use and their load in a much more efficient way, in this way higher frequencies can be reached, even if all the processor cores are being used. A new change especially important in video games, where it is likely that many processing threads will be generated with a light load.

Zen-based cores, the best AMD CPU

In terms of performance, the Zen microarchitecture represents a huge leap in the ability of the kernel to run compared to previous AMD designs, which were based on the Modular Bulldozer architecture and its evolutions (Piledriver, Steamroller and Excavator). The Zen architecture features a 1.75X times larger instruction programming window and 1.5 times greater width and emission resources. This allows Zen to schedule and send more work to the execution units. In addition, a new microoperation cache is included that allows Zen to avoid using the L2 and L3 cache when using frequent access microoperations to improve performance. Products based on the Zen architecture can use SMT technology to increase the number of threads available for the operating system and all software in general.

The Zen cores of these Raven Ridge processors are manufactured using Global Foundries' 14nm + FinFET process, which is a giant leap in energy efficiency compared to the previous Bristol Ridge generation that was manufactured at 28nm. The reduction of the nm allows to integrate more transistors in less space, with this the processors are much more efficient with the energy consumption.

Much more efficient Vega graphics

It is time to look at the graphics section of the Raven Ridge processors, this is in charge of the new AMD Vega GPU architecture, the most advanced version of GCN to date. Vega is the most radical change in AMD's core graphics technology since the introduction of the first GCN-based chips five years ago. The Vega architecture is designed to meet today's needs by adopting several principles: flexible operation, support for large data sets, improved energy efficiency, and extremely scalable performance. This new architecture promises to revolutionize the way GPUs are used in established and emerging markets by offering developers new levels of control, flexibility and scalability.

One of the key goals of the Vega architecture was to achieve higher clock speeds than any previous GCN-based GPU, this required design teams to shut down on higher frequency targets, which involves a certain level of design effort for pretty much every part of the chip.

On some drives like the L1 cache texture decompression data path, teams added more steps to reduce the amount of work done on each clock cycle to meet the goals of increasing the operating frequency. Adding stages is a common means of improving the frequency tolerance of a design.

In other respects, the Vega project required creative design solutions to better balance frequency tolerance with performance per clock. An example of this is the new NCU complex. The design team made major changes to the computing unit to improve its frequency tolerance without compromising its performance.

First, the team changed the fundamental plane of the computing unit. In earlier GCN architectures with less aggressive frequency targets, the presence of connections of a certain length was acceptable because the signals could travel the full distance in a single clock cycle. For this architecture, some of those cable lengths had to be shortened so that signals could traverse them in the span of Vega's much shorter clock cycles. This change required a new physical design for the Vega NCU with an optimized floor plan to allow for shorter joint lengths.

This design change alone was not enough. Key internal units, such as search logic and instruction decoding, were rebuilt with the goal of meeting Vega's stricter runtime objectives. At the same time, the team worked very hard to avoid adding stages to the most performance-critical routes.

V ega also takes advantage of high-performance custom SRAM memories, these SRAMs, modified for use in Vega NCU general registers, offer improvements on multiple fronts, with 8% less delay, 18% savings on area and a 43% reduction in power usage versus standard compiled memories.