A bios review with support for amd ryzen 3000 "zen 2" reveals new overclocking options and tweaks

We have information that MSI and Asus are implemented in the BIOS of their AM4 motherboards. Zen architecture is already a fact, and by mid-2019 this third generation of AMD Ryzen processors with 7mm architecture is expected to officially come out. These processors will be compatible with the AM4 socket and current motherboards, a huge advantage and that is also bringing with it interesting information about these updates in the form of a support code for Zen 2.

The chiplet architecture and its benefits

These updates with AGESA-Combo code 0.0.7.x will allow processors to execute their instructions on current boards with this socket. Already at CES 2019 a prototype of this Ryzen 3000 was presented with a " chiplet " or MCM design that combines the 7nm architecture for the main processing core and 14nm for other integrated circuits within the package. The most important new components in this chip are the PCI-Express controller and the DDR4 Dual Channel memory controller, whose novelties we will talk about in this article.

Without a doubt, the chiplet architecture will allow AMD to implement the pertinent updates to the new Zen 2 while keeping other 14nm components in them. Of course at 7nm the processing core will presumably be built by TSMC, but other components like the memory controller will continue to be built in the 14nm process by GlobalFoundries as it is more cost effective and advantageous. Furthermore, AMD is expected to increase the core density on these chips due to the reduced size of the transistors, thus raising the number to about 12 or 16 cores.

But of course, this architecture in the form of a 3D chiplet implies that the memory controller is not physically integrated into the cores, but that we will find it in a separate module, although always within the same silicon. Intel has already made similar chips in the first generation of the Core "Clarkdale" with 32nm CPUs and a memory controller plus a 45nm GPU.

What is the problem? Well, the connection interface between CPU and controller must be up to the task and not be a bottleneck. Precisely here AMD slacked off in today's Zen with its "Infinity Fabric" bridge. This is why it created the “ Matisse ” bridge that will now offer twice the bandwidth compared to the first Zen generation. This is strictly necessary, because each memory I / O controller must be connected to 8-core CPUs and up to 64 with the "EPYC" server processors.

Updates for Matisse and stability improvements in overclocking

TechpowerUp comes with interesting information about these AGESA 0.0.7.x updates from “1usmus”. A range of new controls and options exclusive to Matisse were found that also hint at the new generation of Ryzen Threadripper processors. In addition, the name " Valhalla " appears in the "common options" section, very present in recent news about these Ryzen 3000. In fact, it could be the code name for these Ryzen AM4 processors and the new chipset that lives to the south bridge to replace the already known X470 with the name of AMD 500.

Another novelty revolves around overclocking RAM memory and this was one of the pending subjects of Infinity Fabric when RAM modules were seriously overlocked. This I / O connection was synchronized with the memory frequency, so when it went too high, the interface could not handle such frequencies. Now the BIOS includes a range of UCLK options with three modes: "Auto", "UCLK == MEMCLK" and " UCLK == MAMCLK / 2 ", the latter being new. The “/ 2” allows the frequency of the I / O bridge to be scaled with respect to the memory, so that there is no need for synchronization between them and thus the frequency can be better synchronized. An example would be to put the RAM at a frequency of 1800 MHz and scale the memory I / O bridge to 1800/2 = 900 MHz.

Also in the acclaimed “Precision Boost Overdrive” important changes have been detected, to make this automatic overclocking algorithm more stable for Zen processors. This algorithm has been improved to make a more precise control over the new CPUs that are coming. These boards were tested with the AGESA 0.0.7.x update together with the AMD 400 CPU and errors were detected in the PBO algorithm and its compatibility with the existing one and compatible with “ Pinnacle Ridge ”. The “ Core Watchdog ” function that recovers the system after an overclocking failure will also take special relevance in these new BIOS updates.

Enhanced memory interface and control options up to PCI-Express Gen 4.0

Matisse will also improve the core control and processing efficiency of the new Zen 3000, controlling the 8 cores of each chip symmetrically, for example 1 + 1, 2 + 2, 3 + 3 or 4 + 4 with 2-core decrements. at every jump, or by directly disabling a full 8-core chip. Recall that AMD CPUs are made up of 8-core chips with 4-core CCX inside. This will optimize the use of the cache and access to main memory.

The " Coherent AMD socket extender " or CAKE has also received an additional configuration called " CAKE CRC Performance Bounds ". In these new Zen 3000s the I / O controller has 100 GB / s IFOP links for each of the 8-core chiplets that make up the silicon. In turn, there is another IFOP of 100 GB / s that connects the chiplets to each other. In this way, the link is more efficient and faster than the Infinity Fabric, and in addition for multi-socket CPUs and up to 64 cores such as Threadrippers, AMD will provide NUMA node controllers per socket with multiple configuration options.

Finally we find another interesting option related to the I / O controller that will allow you to select the generation of PCI-Express up to Gen 4.0. Which gives a good clue that we could soon see a new generation of this interface on our 400 series motherboards.

Without a doubt this Zen 2 generation is highly anticipated in the community, and we see that it is not only about a CPU miniaturization, but much more.

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