Western digital announces risc swerv processor

Western Digital has been working with the RISC-V Open Instruction Set Architecture (ISA), whereby anyone can produce a processor design without paying anything in royalties or license fees. It has finally announced the SweRV RISC-V processor with Open Source license.

New SweRV RISC-V processor with Open Source license

In 2017, the company promised to switch to RISC-V in its storage processing products, with a view to shipping one billion cores in the next two years. Nvidia has also begun moving from proprietary cores to RISC-V to drive input / output on its graphics products, Rambus uses RISC-V for security parts, and has even found its way into SSD storage controllers.

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The core of SweRV itself is a two-way superscalar implementation of the 32-bit variant of the ISA RISC-V, featuring a nine-stage pipeline capable of loading multiple instructions, for simultaneous execution in order. Currently deployed on a 28nm CMOS process node, the kernel runs at up to 1.8GHz and achieves an estimated throughput of 4.9 CoreMarks per megahertz.

Western Digital has confirmed that it plans to not only use SweRV in its own products but also launch it under an open source license. It has already done so with two supporting technologies: the SweRV Instruction Set Simulator (ISS), through which stakeholders can test the kernel; and OmniXtend, which implements consistent cache memory over an Ethernet fabric, focusing on everything from CPUs to GPUs and machine learning coprocessors.

The SweRV will launch in the first quarter of 2019, Western Digital confirmed. What do you think about the announcement of this SweRV RISC-V processor with Open Source license?

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