Jedec updates and improves high bandwidth hbm memories

JEDEC today announced (via a press release) the release of an update to the HBM JESD235 memory standard. HBM DRAM is used in graphics, high-performance computing, server, network, and client applications where maximum bandwidth, bandwidth per watt, and capacity per area are measured as indicators of success. The standard was developed and updated with the support of leading GPU and CPU developers to extend system bandwidth beyond the levels supported by traditional packaged memory.

Updated HBM memory achieves speeds of 307 GB / s bandwidth

The JEDEC JESD235B standard for HBM leverages Wide I / O and TSV technologies to support densities of up to 24GB per device at speeds of up to 307GB / s. This bandwidth is distributed through a 1024-bit wide interface that is divided into 8 independent channels in each DRAM stack. The standard can support 2, 4, 8, and 12 TSV DRAM stacks, with capacities ranging from 1 GB to 24 GB per stack.

This update expands the bandwidth per pin to 2.4 Gbps, adds a new base option to accommodate the 16 Gb per layer and 12 high settings for higher density components, and updates the MISR polynomial options for these new ones. configurations.

AMD is one of the companies that has opted for HBM memory (HBM2 in this case) in the RX VEGA series of graphics cards, but its use extends to other areas as well, more than anything to the professional and business sector.

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