Tiger lake: 10nm chip packs 50% more l3 cache
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Tiger Lake-U will present a 50% increase in L3 cache capacity, which will go from 8MB to 12MB, due to the posting of a processor dump by @ InstLatX64 on Twitter. This means an increase of up to 3MB of L3 cache per core.
Tiger Lake-U will present a 50% increase in L3 cache capacity
As expected, the Tiger Lake-U model is a 4-core processor with HyperThreading. The published image also reveals that the engineering sample runs at 3.4GHz, a respectable frequency for a pre-production model.
The image also contains a bunch of flags representing the supported instruction sets. It confirms AVX-512 support as Sunny Cove, but doesn't seem to have the avx512_bf flag that would be expected if it had supported bfloat16 like Cooper Lake Xeon processors from early next year.
The dump shows that the quad-core Tiger Lake-U has 12MB of total L3 cache, a 50% increase. This fits in with the cache redesign Intel had revealed for Willow Cove, Tiger Lake's CPU core, though the cache redesign is likely to involve changes greater than a simple size increase. For example, a larger cache has a higher latency, so there is likely to be some lower adjustment to the capo.
Tiger Lake is set to be released next year. These processors will also feature the Gen12 'Xe' integrated graphics, which will have a new display function and a major instruction set update. We will keep you informed.
Tomshardware fontTiger lake, intel would increase the amount of cache of these cpus
This information comes from a listing in Geekbench's online database of a Tiger Lake-Y processor.
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