Toshiba already develops 5-bit-per-cell (plc) flash ssd technology
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Toshiba has already begun planning for future BiCS Flash generations. Each new generation will coincide with the new generations of the PCIe standard, starting with BiCS 5, which will soon be released in alignment with PCIe 4.0, but the company has not provided a specific timeline. BiCS5 will have a greater bandwidth of 1, 200MT / s, while BiCS6 will reach 1, 600MT / s, and BiCS7 is expected to reach 2, 000MT / s.
Toshiba already develops 5-bit-per-cell (PLC) Flash SSD technology
The company has also begun researching Penta-level cell (PLC) NAND flash technology and verified the operation of five-bit-per-cell NAND technology by modifying its current NAND QLC. The new flash provides more density with the ability to store five bits per cell, instead of just four that is present in the current QLC. But, to do this, the cell needs to be able to store 32 different voltage levels, and the SSD drivers need to read them accurately. With so many voltage levels to read and write on a metric scale, new technology is a big challenge. To control the stricter thresholds, the company had to develop some additional processes that could be adapted to its current TLC and QLC to increase performance.
QLC is already quite slow and has less resistance than other types of flash. The PLC will have even less resistance and slower performance. However, new NVMe protocol features like Zoned Namespaces (ZNS) should help mitigate some of the problems. ZNS by itself aims to reduce write amplification, reduce the need for media over-provisioning and the use of internal controller DRAMs, and of course improve performance and latency.
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The company has developed a new process that increases the density of matrices in the next generations of BiCS FLASH in all its forms. Essentially, it will divide the memory cell in half to expand it while retaining the normal 3D flash process. Toshiba is not sure that this approach is fully feasible at the moment.
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