Tsmc reveals wafer-on chip stacking technology

TSMC has taken advantage of the company's Technology Symposium to announce its new Wafer-on-Wafer (WoW) technology, a 3D stacking technique for silicon wafers, which allows you to connect chips to two silicon wafers using through-silicone connections via (TSV), similar to 3D NAND technology.

TSMC announces its revolutionary Wafer-on-Wafer technique

This WoM technology from TSMC can connect two matrices directly and with a minimum of data transfer thanks to the small distance between the chips, this allows for better performance and a much more compact final package. The WoW technique stacks silicon while it is still inside its original wafer, offering advantages and disadvantages. This is a major difference from what we see today with multi-die silicon technologies, which have multiple dies sitting next to each other on an interposer, or using Intel's EMIB technology.

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The advantage is that this technology can connect two die wafers at the same time, offering much less parallelization within the manufacturing process and the possibility of lower final costs. The problem arises when joining failed silicon with active silicon in the second layer, which reduces overall performance. A problem that prevents this technology from being viable to manufacture silicon that offer wafer-by-wafer-based yields of less than 90%.

Another potential problem occurs when two pieces of silicon that produce heat are stacked, creating a situation where the density of heat could become a limiting factor. This thermal limitation makes WoW technology more suitable for silicons with low energy consumption, and therefore little heat.

Direct WoW connectivity enables silicon to communicate exceptionally quickly and with minimal latencies, the only question is whether it will one day be viable in high-performance products.

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